This application is based upon and claims priority from Korean Patent Application No. 99-38314 filed Sep. 9, 1999, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device and, more particularly, to a method of planarizing an insulating layer using a chemical-mechanical polishing (CMP) method.
2. Description of the Related Art
As semiconductor devices become more highly integrated and as multilayer wiring structures are needed, the reduction of the dielectric constant of an interlayer insulating layer is required. To satisfy such a requirement, it has been suggested that a low-k dielectric material with a low-k dielectric constant be used for the interlayer insulating layer. Moreover, the interlayer insulating layer requires a high degree of flatness. To meet this requirement, it has been suggested that a polishing process using a chemical-mechanical polishing (CMP) process be used.
However, the CMP process is often accompanied by a dishing phenomenon. To prevent this phenomenon, the formation of a polishing stop layer on an insulating layer or between layers of an insulating layer having a multi-layer structure has been suggested.
A feature of the present invention provides a method of planarization of an insulating layer of a semiconductor device, wherein an interlayer insulating layer is formed from an organic material having a low dielectric constant. A chemical-mechanical polishing (CMP) method is used to obtain a flat surface.
To achieve this feature of the present invention, a method of planarization of an insulating layer of a semiconductor device is provided. The first step in the method according to the present invention is to prepare a semiconductor substrate having a stepped surface due to material layer patterns of various sizes on the surface thereof. An interlayer insulating layer is formed of an organic material which generally has a low dielectric constant. The interlayer insulating layer covers the stepped surface of the semiconductor substrate. A capping insulating layer is formed on the interlayer insulating layer. A portion of the interlayer insulating layer which rises above the other portion of the interlayer insulating layer is selectively exposed by performing a partial chemical-mechanical polishing process side of the capping insulating layer. The exposed portion of the interlayer insulating layer is plasma-processed to a preset depth. An entirely planarized interlayer insulating layer is formed by performing a blanket chemical-mechanical polishing process on the plasma processed portion of the interlayer insulating layer and the remaining capping insulating layer. A silicon-methyl group bond is transformed into a silicon-hydroxide group bond by the plasma process in the exposed surface of the low dielectric material.
According to the present invention, the higher rise of the transformed interlayer insulating layer formed of the organic material is rapidly polished by selectively performing the plasma process, thereby realizing global planarization of the interlayer insulating layer.